1. Field of the Invention
The present invention relates to the structure of a semiconductor device and a manufacturing method thereof, and more especially relates to the structure of a Dynamic-Threshold Voltage MOSFET (DTMOSFET) built on a Silicon-On-Insulator (SOI) substrate and a manufacturing method thereof.
2. Description of the Background Art
Among MOSFETs on SOI, DTMOSFETs (hereinafter referred to as xe2x80x9cDTMOSsxe2x80x9d) have been proposed as means for increasing operating speed. FIG. 42 is a cross-sectional view schematically showing the structure of a conventional DTMOS on SOI (cf. Assaderaghi et al., xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d, IEDM 94-811, FIG. 1a). An SOI substrate 101 has a multilayer structure with a silicon substrate 102, a buried oxide film 103, and an SOI layer 104 stacked in this order. On the upper surface of the SOI layer 104, a multilayer gate structure is selectively formed, wherein a gate oxide film 105 and a gate electrode 106 are stacked in this order. In the upper surface of the SOI layer 104, a pair of source/drain regions 108 are formed to sandwich a body region 107 located under the gate structure. The gate electrode 106 and the body region 107 are electrically connected to each other.
FIG. 43 is a graph showing the relationships between body potential VB and operating threshold voltage VTH of a DTMOS transistor taken as an NMOS. When the transistor is turned on with a HIGH on the gate, the body potential VB correspondingly goes HIGH. This lowers the operating threshold voltage VTH as shown in FIG. 43, resulting in a larger current flow than a standard MOSFET on SOI.
FIG. 44 is a top view specifically showing the structure of the DTMOS in FIG. 42, and FIG. 45 is a cross-sectional view of the DTMOS in FIG. 44 taken along the line X1 (cf. Assaderaghi et al., xe2x80x9cA Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operationxe2x80x9d, IEDM94-811, FIG. 1b). The gate electrode 106 includes an electrode portion 106A above the body region 107 sandwitched between the pair of source/drain regions 108, and a wider pad portion 106B connected to the electrode portion 106A. An element isolation insulation film 109 is formed by LOCOS to surround the source/drain regions 108 and the pad portion 106B. The bottom surface of the element isolation insulation film 109 reaches the upper surface of the buried oxide film 103. That is, the element isolation insulation film 109 achieves so-called xe2x80x9ccomplete isolationxe2x80x9d. In the middle of the pad portion 106B, a conductor-filled contact hole 110 is formed, extending through the gate oxide film 105 to the upper surface of the SOI layer 104. A conductor 112 filling the contact hole 110, such as Al, provides electrical connections between the gate electrode 106 and a p+-type region 111 which is selectively formed in the body region 107.
In such a conventional DTMOS, however, there is only a small distance between the pad portion 106B and the SOI layer 104 (body region 107). This causes high parastic capacitance therebetween, which is added to gate capacitance, thereby increasing delay in operation.
A first aspect of the present invention is directed to a semiconductor device comprising: an SOI substrate having a multilayer structure with a semiconductor substrate, an insulating layer, and a semiconductor layer stacked in this order; a first element isolation insulation film formed in an upper surface of the semiconductor layer to a predetermined depth that does not reach an upper surface of the insulating layer, in an element isolation region of the SOI substrate; a gate insulation film formed on the upper surface of the semiconductor layer in an element forming region of the SOI substrate; a gate electrode formed on the gate insulation film and the first element isolation insulation film; an interlayer insulation film formed on the gate electrode and the first element isolation insulation film; and a contact hole filled with a conductor, which is selectively formed in an upper surface of the interlayer insulation film, extending through the interlayer insulation film and the first element isolation insulation film to the upper surface of the semiconductor layer in the element isolation region of the SOI substrate, the conductor being in contact with the gate electrode on the first element isolation insulation film.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the gate electrode is formed so that its sidewall is on the first element isolation insulation film; and the conductor is in contact with the sidewall of the gate electrode.
According to a third aspect of the present invention, the semiconductor device of the first aspect further comprises: an impurity region formed in the part of the upper surface of the semiconductor layer that is in contact with the contact hole, the impurity region having a higher impurity concentration than the semiconductor layer.
According to a fourth aspect of the present invention, the semiconductor device of the first aspect includes a plurality of semiconductor devices and further comprises: a second element isolation insulation film extending from the upper surface of the semiconductor layer to the upper surface of the insulating layer, between adjacent ones of the semiconductor devices.
A fifth aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: (a) preparing an SOI substrate having a multilayer structure with a semiconductor substrate, an insulating layer, and a semiconductor layer stacked in this order; (b) forming a first element isolation insulation film in an upper surface of the semiconductor layer to a predetermined depth that does not reach an upper surface of the insulating layer, in an element isolation region of the SOI substrate; (c) forming a gate insulation film on the upper surface of the semiconductor layer in an element forming region of the SOI substrate; (d) forming a gate electrode on the gate insulation film and the first element isolation insulation film; (e) forming an interlayer insulation film on the gate electrode and the first element isolation insulation film; (f) selectively forming a contact hole in an upper surface of the interlayer insulation film, extending through the first element isolation insulation film to the upper surface of the semiconductor layer, in the element isolation region of the SOI substrate, the contact hole being in contact with the gate electrode on the first element isolation insulation film; and (g) filling the contact hole with a conductor.
According to a sixth aspect of the present invention, the method of the fifth aspect further comprises the step of: (h) between the steps (f) and (g), forming an impurity region with a higher impurity concentration than the semiconductor layer, by introducing impurities into the upper surface of the semiconductor layer through the contact hole.
According to a seventh aspect of the present invention, the method of the fifth aspect further comprises the step of: (i) before the step (f), forming an insulation film between a bottom surface of the first element isolation insulation film and the upper surface of the semiconductor layer, the insulation film being made with a material different from the first element isolation insulation film. The step (f) includes the steps of: (f-1) selectively removing the interlayer insulation film and the first element isolation insulation film, using the insulation film as an etching stopper; and (f-2) removing the insulation film exposed in the step (f-1).
According to an eighth aspect of the present invention, in the method of the fifth aspect, the step (b) includes the steps of: (b-1) forming a recessed portion by removing the upper surface of the semiconductor layer in the element isolation region by anisotropic etching having a high etch rate in a depth direction of the SOI substrate; and (b-2) forming the first element isolation insulation film to fill the recessed portion.
According to a ninth aspect of the present invention, in the method of the fifth aspect, the semiconductor includes a plurality of semiconductor devices. The method further comprises the step of: (j) forming a second element isolation insulation film extending from the upper surface of the semiconductor layer to the upper surface of the insulating layer, between adjacent ones of the semiconductor devices, wherein the step (b) and (j) are performed by the steps of: (x-1) forming a first recessed portion by removing the upper surface of the semiconductor layer in the element isolation region to a depth that does not reach the upper surface of the insulating layer; (x-2) forming a second recessed portion reaching the upper surface of the insulating layer, by selectively removing a bottom surface of the first recessed portion; and (x-3) filling the first and second recessed portions with insulation films.
In the semiconductor device of the first aspect, an increased distance between the gate electrode and the semiconductor layer by the presence of the first element isolation insulation film therebetween reduces parasitic capacitance therebetween, thus suppressing delay in operation.
The semiconductor device of the second aspect can reduce the area of the gate electrode for the contact hole, as compared to the device wherein the contact hole for establishing electrical connections between the gate electrode and the semiconductor layer is formed in the middle of the gate electrode.
The semiconductor device of the third aspect can reduce contact resistance between the semiconductor layer and the conductor which fills the contact hole.
In the semiconductor device of the fourth aspect, the second element isolation insulation film achieves complete electrical isolation between adjacent semiconductor devices. This makes it possible to appropriately prevent the occurrence of leakage current and latch-up in the operation of the semiconductor device.
In the method of the fifth aspect, an increased distance between the semiconductor layer and the gate electrode by the presence of the first element isolation insulation film therebetween reduces parasitic capacitance therebetween, thus suppressing delay in operation.
In the method of the sixth aspect, it is possible to reduce contact resistance between the semiconductor layer and the conductor which fills the contact hole.
In the method of the seventh aspect, the contact hole does not reach the insulating layer through the semiconductor layer even if the semiconductor layer between the bottom surface of the first element isolation insulation film and the upper surface of the semiconductor layer has a small film thickness. This ensures electrical connections between the gate electrode and the semiconductor layer.
In the method of the eighth aspect, the occurrence of bird""s beak can be minimized as compared to the method wherein the first element isolation insulation film is formed by LOCOS. This allows reduction in device dimension.
In the method of the ninth aspect, the second element isolation insulation film achieves complete electrical isolation between adjacent semiconductor devices. This makes it possible to appropriately prevent the occurrence of leakage current and latch-up in the operation of the semiconductor device.
An object of the present invention is to provide a semiconductor device capable of suppressing delay in operation by reducing parasitic capacitance between the pad portion of the gate electrode and the body region of DTMOS on the SOI substrate, and a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.